/*
 * File:           C:\Users\dell\Desktop\ADI project\QC20\MCU_FILE_FOR_QC20_384K\ADAU1787_IC_1_FAST.h
 *
 * Created:        Thursday, April 1, 2021 5:04:05 PM
 * Description:    QC20-384K:IC 1-Fast program data.
 *
 * This software is distributed in the hope that it will be useful,
 * but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
 * CONDITIONS OF ANY KIND, without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 *
 * This software may only be used to program products purchased from
 * Analog Devices for incorporation by you into audio products that
 * are intended for resale to audio product end users. This software
 * may not be distributed whole or in any part to third parties.
 *
 * Copyright ©2021 Analog Devices, Inc. All rights reserved.
 */
#ifndef __ADAU1787_IC_1_FAST_H__
#define __ADAU1787_IC_1_FAST_H__

#include "SigmaStudioFW.h"
#include "ADAU1787_IC_1_FAST_REG.h"

#define DEVICE_ARCHITECTURE_IC_1_FAST             "ADAU1787F"
#define DEVICE_ADDR_IC_1_FAST                     0x50

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKA0_ADDR_IC_1_Fast 53848
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKA0_ADDR_IC_1_Fast 54104
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKA0_ADDR_IC_1_Fast 54360
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKA0_ADDR_IC_1_Fast 54616
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKA0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKA0_ADDR_IC_1_Fast 53592
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKA0_SIZE_IC_1_Fast] = {
0xD1, 0xA4, 0x67, 0xD0, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKB0_ADDR_IC_1_Fast 55128
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKB0_ADDR_IC_1_Fast 55384
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKB0_ADDR_IC_1_Fast 55640
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKB0_ADDR_IC_1_Fast 55896
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKB0_ADDR_IC_1_Fast 54872
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKB0_SIZE_IC_1_Fast] = {
0xD1, 0xA4, 0x67, 0xD0, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKC0_ADDR_IC_1_Fast 56408
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF0BANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKC0_ADDR_IC_1_Fast 56664
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF1BANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKC0_ADDR_IC_1_Fast 56920
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF2BANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKC0_ADDR_IC_1_Fast 57176
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1COEFF3BANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKC0_ADDR_IC_1_Fast 56152
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG1SOURCEADDRESSBANKC0_SIZE_IC_1_Fast] = {
0xD1, 0xA4, 0x67, 0xD0, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKA0_ADDR_IC_1_Fast 53856
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKA0_ADDR_IC_1_Fast 54112
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKA0_ADDR_IC_1_Fast 54368
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKA0_ADDR_IC_1_Fast 54624
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKA0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKA0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKA0_ADDR_IC_1_Fast 53600
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKA0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKA0_SIZE_IC_1_Fast] = {
0xD5, 0xAC, 0x6F, 0xD0, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKB0_ADDR_IC_1_Fast 55136
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKB0_ADDR_IC_1_Fast 55392
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKB0_ADDR_IC_1_Fast 55648
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKB0_ADDR_IC_1_Fast 55904
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKB0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKB0_ADDR_IC_1_Fast 54880
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKB0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKB0_SIZE_IC_1_Fast] = {
0xD5, 0xAC, 0x6F, 0xD0, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKC0_ADDR_IC_1_Fast 56416
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF0BANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKC0_ADDR_IC_1_Fast 56672
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF1BANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKC0_ADDR_IC_1_Fast 56928
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF2BANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKC0_ADDR_IC_1_Fast 57184
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2COEFF3BANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKC0_SIZE_IC_1_Fast 4
#define MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKC0_ADDR_IC_1_Fast 56160
const ADI_REG_TYPE MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKC0_Data_IC_1_Fast[MULTCTRLLINMIXERPEREGRINEALG2SOURCEADDRESSBANKC0_SIZE_IC_1_Fast] = {
0xD5, 0xAC, 0x6F, 0xD0, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKA0_ADDR_IC_1_Fast 53524
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x89, 0x16, 0x37, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKA0_ADDR_IC_1_Fast 53780
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKA0_SIZE_IC_1_Fast] = {
0xFA, 0xF5, 0x57, 0x34, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKA0_ADDR_IC_1_Fast 54036
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x81, 0xA5, 0xDA, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKA0_ADDR_IC_1_Fast 54292
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKA0_SIZE_IC_1_Fast] = {
0x0F, 0xF1, 0x6C, 0x5D, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKA0_ADDR_IC_1_Fast 54548
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKA0_SIZE_IC_1_Fast] = {
0xF8, 0x0E, 0x56, 0xB5, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKB0_ADDR_IC_1_Fast 54804
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKB0_ADDR_IC_1_Fast 55060
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKB0_ADDR_IC_1_Fast 55316
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKB0_ADDR_IC_1_Fast 55572
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKB0_ADDR_IC_1_Fast 55828
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKC0_ADDR_IC_1_Fast 56084
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKC0_ADDR_IC_1_Fast 56340
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKC0_ADDR_IC_1_Fast 56596
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKC0_ADDR_IC_1_Fast 56852
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKC0_ADDR_IC_1_Fast 57108
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKA1_ADDR_IC_1_Fast 53528
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKA1_SIZE_IC_1_Fast] = {
0x07, 0xF8, 0xF6, 0x26, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKA1_ADDR_IC_1_Fast 53784
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKA1_SIZE_IC_1_Fast] = {
0xF0, 0x14, 0x98, 0x82, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKA1_ADDR_IC_1_Fast 54040
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKA1_SIZE_IC_1_Fast] = {
0x07, 0xF2, 0x73, 0x87, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKA1_ADDR_IC_1_Fast 54296
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKA1_SIZE_IC_1_Fast] = {
0x0F, 0xEB, 0x67, 0x7E, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKA1_ADDR_IC_1_Fast 54552
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKA1_SIZE_IC_1_Fast] = {
0xF8, 0x14, 0x96, 0x53, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKB1_ADDR_IC_1_Fast 54808
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKB1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKB1_ADDR_IC_1_Fast 55064
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKB1_ADDR_IC_1_Fast 55320
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKB1_ADDR_IC_1_Fast 55576
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKB1_ADDR_IC_1_Fast 55832
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKC1_ADDR_IC_1_Fast 56088
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKC1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKC1_ADDR_IC_1_Fast 56344
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKC1_ADDR_IC_1_Fast 56600
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKC1_ADDR_IC_1_Fast 56856
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKC1_ADDR_IC_1_Fast 57112
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKA2_ADDR_IC_1_Fast 53532
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKA2_SIZE_IC_1_Fast] = {
0x07, 0xDF, 0xE4, 0x8B, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKA2_ADDR_IC_1_Fast 53788
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKA2_SIZE_IC_1_Fast] = {
0xF0, 0x60, 0x64, 0x95, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKA2_ADDR_IC_1_Fast 54044
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKA2_SIZE_IC_1_Fast] = {
0x07, 0xC1, 0x2C, 0x26, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKA2_ADDR_IC_1_Fast 54300
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKA2_SIZE_IC_1_Fast] = {
0x0F, 0x9F, 0x9B, 0x6B, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKA2_ADDR_IC_1_Fast 54556
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKA2_SIZE_IC_1_Fast] = {
0xF8, 0x5E, 0xEF, 0x4F, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKB2_ADDR_IC_1_Fast 54812
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKB2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKB2_ADDR_IC_1_Fast 55068
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKB2_ADDR_IC_1_Fast 55324
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKB2_ADDR_IC_1_Fast 55580
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKB2_ADDR_IC_1_Fast 55836
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKC2_ADDR_IC_1_Fast 56092
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKC2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKC2_ADDR_IC_1_Fast 56348
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKC2_ADDR_IC_1_Fast 56604
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKC2_ADDR_IC_1_Fast 56860
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKC2_ADDR_IC_1_Fast 57116
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKA3_ADDR_IC_1_Fast 53536
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKA3_SIZE_IC_1_Fast] = {
0x07, 0x01, 0xDC, 0x6C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKA3_ADDR_IC_1_Fast 53792
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKA3_SIZE_IC_1_Fast] = {
0xF2, 0x4B, 0xDD, 0x64, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKA3_ADDR_IC_1_Fast 54048
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKA3_SIZE_IC_1_Fast] = {
0x06, 0xBD, 0x4D, 0xD7, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKA3_ADDR_IC_1_Fast 54304
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKA3_SIZE_IC_1_Fast] = {
0x0D, 0xB4, 0x22, 0x9C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKA3_ADDR_IC_1_Fast 54560
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKA3_SIZE_IC_1_Fast] = {
0xFA, 0x40, 0xD5, 0xBE, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKB3_ADDR_IC_1_Fast 54816
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKB3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKB3_ADDR_IC_1_Fast 55072
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKB3_ADDR_IC_1_Fast 55328
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKB3_ADDR_IC_1_Fast 55584
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKB3_ADDR_IC_1_Fast 55840
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKC3_ADDR_IC_1_Fast 56096
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKC3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKC3_ADDR_IC_1_Fast 56352
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKC3_ADDR_IC_1_Fast 56608
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKC3_ADDR_IC_1_Fast 56864
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKC3_ADDR_IC_1_Fast 57120
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKA4_ADDR_IC_1_Fast 53540
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKA4_SIZE_IC_1_Fast] = {
0x05, 0x5F, 0x47, 0x73, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKA4_ADDR_IC_1_Fast 53796
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKA4_SIZE_IC_1_Fast] = {
0xF7, 0x62, 0x09, 0xE7, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKA4_ADDR_IC_1_Fast 54052
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKA4_SIZE_IC_1_Fast] = {
0x03, 0x74, 0x98, 0x91, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKA4_ADDR_IC_1_Fast 54308
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKA4_SIZE_IC_1_Fast] = {
0x0D, 0x67, 0x6C, 0x87, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKA4_ADDR_IC_1_Fast 54564
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKA4_SIZE_IC_1_Fast] = {
0xFA, 0x62, 0xA9, 0x8F, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKB4_ADDR_IC_1_Fast 54820
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKB4_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKB4_ADDR_IC_1_Fast 55076
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKB4_ADDR_IC_1_Fast 55332
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKB4_ADDR_IC_1_Fast 55588
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKB4_ADDR_IC_1_Fast 55844
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN10BBANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN10BBANKC4_ADDR_IC_1_Fast 56100
const ADI_REG_TYPE EQ1787SINGLECHAN10BBANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN10BBANKC4_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11BBANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11BBANKC4_ADDR_IC_1_Fast 56356
const ADI_REG_TYPE EQ1787SINGLECHAN11BBANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN11BBANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12BBANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12BBANKC4_ADDR_IC_1_Fast 56612
const ADI_REG_TYPE EQ1787SINGLECHAN12BBANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN12BBANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN11ABANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN11ABANKC4_ADDR_IC_1_Fast 56868
const ADI_REG_TYPE EQ1787SINGLECHAN11ABANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN11ABANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN12ABANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN12ABANKC4_ADDR_IC_1_Fast 57124
const ADI_REG_TYPE EQ1787SINGLECHAN12ABANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN12ABANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKA0_ADDR_IC_1_Fast 53568
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x89, 0x16, 0x37, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKA0_ADDR_IC_1_Fast 53824
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKA0_SIZE_IC_1_Fast] = {
0xFA, 0xF5, 0x57, 0x34, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKA0_ADDR_IC_1_Fast 54080
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x81, 0xA5, 0xDA, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKA0_ADDR_IC_1_Fast 54336
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKA0_SIZE_IC_1_Fast] = {
0x0F, 0xF1, 0x6C, 0x5D, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKA0_ADDR_IC_1_Fast 54592
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKA0_SIZE_IC_1_Fast] = {
0xF8, 0x0E, 0x56, 0xB5, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKB0_ADDR_IC_1_Fast 54848
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKB0_ADDR_IC_1_Fast 55104
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKB0_ADDR_IC_1_Fast 55360
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKB0_ADDR_IC_1_Fast 55616
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKB0_ADDR_IC_1_Fast 55872
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKC0_ADDR_IC_1_Fast 56128
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKC0_ADDR_IC_1_Fast 56384
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKC0_ADDR_IC_1_Fast 56640
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKC0_ADDR_IC_1_Fast 56896
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKC0_ADDR_IC_1_Fast 57152
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKA1_ADDR_IC_1_Fast 53572
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKA1_SIZE_IC_1_Fast] = {
0x07, 0xF8, 0xF6, 0x26, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKA1_ADDR_IC_1_Fast 53828
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKA1_SIZE_IC_1_Fast] = {
0xF0, 0x14, 0x98, 0x82, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKA1_ADDR_IC_1_Fast 54084
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKA1_SIZE_IC_1_Fast] = {
0x07, 0xF2, 0x73, 0x87, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKA1_ADDR_IC_1_Fast 54340
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKA1_SIZE_IC_1_Fast] = {
0x0F, 0xEB, 0x67, 0x7E, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKA1_ADDR_IC_1_Fast 54596
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKA1_SIZE_IC_1_Fast] = {
0xF8, 0x14, 0x96, 0x53, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKB1_ADDR_IC_1_Fast 54852
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKB1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKB1_ADDR_IC_1_Fast 55108
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKB1_ADDR_IC_1_Fast 55364
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKB1_ADDR_IC_1_Fast 55620
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKB1_ADDR_IC_1_Fast 55876
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKC1_ADDR_IC_1_Fast 56132
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKC1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKC1_ADDR_IC_1_Fast 56388
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKC1_ADDR_IC_1_Fast 56644
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKC1_ADDR_IC_1_Fast 56900
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKC1_ADDR_IC_1_Fast 57156
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKA2_ADDR_IC_1_Fast 53576
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKA2_SIZE_IC_1_Fast] = {
0x07, 0xDF, 0xE4, 0x8B, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKA2_ADDR_IC_1_Fast 53832
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKA2_SIZE_IC_1_Fast] = {
0xF0, 0x60, 0x64, 0x95, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKA2_ADDR_IC_1_Fast 54088
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKA2_SIZE_IC_1_Fast] = {
0x07, 0xC1, 0x2C, 0x26, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKA2_ADDR_IC_1_Fast 54344
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKA2_SIZE_IC_1_Fast] = {
0x0F, 0x9F, 0x9B, 0x6B, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKA2_ADDR_IC_1_Fast 54600
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKA2_SIZE_IC_1_Fast] = {
0xF8, 0x5E, 0xEF, 0x4F, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKB2_ADDR_IC_1_Fast 54856
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKB2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKB2_ADDR_IC_1_Fast 55112
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKB2_ADDR_IC_1_Fast 55368
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKB2_ADDR_IC_1_Fast 55624
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKB2_ADDR_IC_1_Fast 55880
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKC2_ADDR_IC_1_Fast 56136
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKC2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKC2_ADDR_IC_1_Fast 56392
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKC2_ADDR_IC_1_Fast 56648
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKC2_ADDR_IC_1_Fast 56904
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKC2_ADDR_IC_1_Fast 57160
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKA3_ADDR_IC_1_Fast 53580
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKA3_SIZE_IC_1_Fast] = {
0x07, 0x01, 0xDC, 0x6C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKA3_ADDR_IC_1_Fast 53836
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKA3_SIZE_IC_1_Fast] = {
0xF2, 0x4B, 0xDD, 0x64, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKA3_ADDR_IC_1_Fast 54092
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKA3_SIZE_IC_1_Fast] = {
0x06, 0xBD, 0x4D, 0xD7, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKA3_ADDR_IC_1_Fast 54348
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKA3_SIZE_IC_1_Fast] = {
0x0D, 0xB4, 0x22, 0x9C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKA3_ADDR_IC_1_Fast 54604
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKA3_SIZE_IC_1_Fast] = {
0xFA, 0x40, 0xD5, 0xBE, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKB3_ADDR_IC_1_Fast 54860
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKB3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKB3_ADDR_IC_1_Fast 55116
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKB3_ADDR_IC_1_Fast 55372
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKB3_ADDR_IC_1_Fast 55628
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKB3_ADDR_IC_1_Fast 55884
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKC3_ADDR_IC_1_Fast 56140
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKC3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKC3_ADDR_IC_1_Fast 56396
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKC3_ADDR_IC_1_Fast 56652
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKC3_ADDR_IC_1_Fast 56908
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKC3_ADDR_IC_1_Fast 57164
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKA4_ADDR_IC_1_Fast 53584
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKA4_SIZE_IC_1_Fast] = {
0x05, 0x5F, 0x47, 0x73, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKA4_ADDR_IC_1_Fast 53840
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKA4_SIZE_IC_1_Fast] = {
0xF7, 0x62, 0x09, 0xE7, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKA4_ADDR_IC_1_Fast 54096
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKA4_SIZE_IC_1_Fast] = {
0x03, 0x74, 0x98, 0x91, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKA4_ADDR_IC_1_Fast 54352
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKA4_SIZE_IC_1_Fast] = {
0x0D, 0x67, 0x6C, 0x87, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKA4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKA4_ADDR_IC_1_Fast 54608
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKA4_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKA4_SIZE_IC_1_Fast] = {
0xFA, 0x62, 0xA9, 0x8F, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKB4_ADDR_IC_1_Fast 54864
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKB4_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKB4_ADDR_IC_1_Fast 55120
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKB4_ADDR_IC_1_Fast 55376
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKB4_ADDR_IC_1_Fast 55632
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKB4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKB4_ADDR_IC_1_Fast 55888
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKB4_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKB4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN20BBANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN20BBANKC4_ADDR_IC_1_Fast 56144
const ADI_REG_TYPE EQ1787SINGLECHAN20BBANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN20BBANKC4_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21BBANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21BBANKC4_ADDR_IC_1_Fast 56400
const ADI_REG_TYPE EQ1787SINGLECHAN21BBANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN21BBANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22BBANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22BBANKC4_ADDR_IC_1_Fast 56656
const ADI_REG_TYPE EQ1787SINGLECHAN22BBANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN22BBANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN21ABANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN21ABANKC4_ADDR_IC_1_Fast 56912
const ADI_REG_TYPE EQ1787SINGLECHAN21ABANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN21ABANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN22ABANKC4_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN22ABANKC4_ADDR_IC_1_Fast 57168
const ADI_REG_TYPE EQ1787SINGLECHAN22ABANKC4_Data_IC_1_Fast[EQ1787SINGLECHAN22ABANKC4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3SOURCEADDRESSBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG3SOURCEADDRESSBANKA0_ADDR_IC_1_Fast 53520
const ADI_REG_TYPE MUTEALG3SOURCEADDRESSBANKA0_Data_IC_1_Fast[MUTEALG3SOURCEADDRESSBANKA0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG3ZC_LDB_RAMPDWNBANKA0_ADDR_IC_1_Fast 54032
const ADI_REG_TYPE MUTEALG3ZC_LDB_RAMPDWNBANKA0_Data_IC_1_Fast[MUTEALG3ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3RAMPUPBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG3RAMPUPBANKA0_ADDR_IC_1_Fast 54288
const ADI_REG_TYPE MUTEALG3RAMPUPBANKA0_Data_IC_1_Fast[MUTEALG3RAMPUPBANKA0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x04, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3GAIN_TARGETBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG3GAIN_TARGETBANKA0_ADDR_IC_1_Fast 54544
const ADI_REG_TYPE MUTEALG3GAIN_TARGETBANKA0_Data_IC_1_Fast[MUTEALG3GAIN_TARGETBANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3SOURCEADDRESSBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG3SOURCEADDRESSBANKB0_ADDR_IC_1_Fast 54800
const ADI_REG_TYPE MUTEALG3SOURCEADDRESSBANKB0_Data_IC_1_Fast[MUTEALG3SOURCEADDRESSBANKB0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG3ZC_LDB_RAMPDWNBANKB0_ADDR_IC_1_Fast 55312
const ADI_REG_TYPE MUTEALG3ZC_LDB_RAMPDWNBANKB0_Data_IC_1_Fast[MUTEALG3ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3RAMPUPBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG3RAMPUPBANKB0_ADDR_IC_1_Fast 55568
const ADI_REG_TYPE MUTEALG3RAMPUPBANKB0_Data_IC_1_Fast[MUTEALG3RAMPUPBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3GAIN_TARGETBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG3GAIN_TARGETBANKB0_ADDR_IC_1_Fast 55824
const ADI_REG_TYPE MUTEALG3GAIN_TARGETBANKB0_Data_IC_1_Fast[MUTEALG3GAIN_TARGETBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3SOURCEADDRESSBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG3SOURCEADDRESSBANKC0_ADDR_IC_1_Fast 56080
const ADI_REG_TYPE MUTEALG3SOURCEADDRESSBANKC0_Data_IC_1_Fast[MUTEALG3SOURCEADDRESSBANKC0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG3ZC_LDB_RAMPDWNBANKC0_ADDR_IC_1_Fast 56592
const ADI_REG_TYPE MUTEALG3ZC_LDB_RAMPDWNBANKC0_Data_IC_1_Fast[MUTEALG3ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3RAMPUPBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG3RAMPUPBANKC0_ADDR_IC_1_Fast 56848
const ADI_REG_TYPE MUTEALG3RAMPUPBANKC0_Data_IC_1_Fast[MUTEALG3RAMPUPBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG3GAIN_TARGETBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG3GAIN_TARGETBANKC0_ADDR_IC_1_Fast 57104
const ADI_REG_TYPE MUTEALG3GAIN_TARGETBANKC0_Data_IC_1_Fast[MUTEALG3GAIN_TARGETBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4SOURCEADDRESSBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG4SOURCEADDRESSBANKA0_ADDR_IC_1_Fast 53564
const ADI_REG_TYPE MUTEALG4SOURCEADDRESSBANKA0_Data_IC_1_Fast[MUTEALG4SOURCEADDRESSBANKA0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG4ZC_LDB_RAMPDWNBANKA0_ADDR_IC_1_Fast 54076
const ADI_REG_TYPE MUTEALG4ZC_LDB_RAMPDWNBANKA0_Data_IC_1_Fast[MUTEALG4ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4RAMPUPBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG4RAMPUPBANKA0_ADDR_IC_1_Fast 54332
const ADI_REG_TYPE MUTEALG4RAMPUPBANKA0_Data_IC_1_Fast[MUTEALG4RAMPUPBANKA0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x04, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4GAIN_TARGETBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG4GAIN_TARGETBANKA0_ADDR_IC_1_Fast 54588
const ADI_REG_TYPE MUTEALG4GAIN_TARGETBANKA0_Data_IC_1_Fast[MUTEALG4GAIN_TARGETBANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4SOURCEADDRESSBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG4SOURCEADDRESSBANKB0_ADDR_IC_1_Fast 54844
const ADI_REG_TYPE MUTEALG4SOURCEADDRESSBANKB0_Data_IC_1_Fast[MUTEALG4SOURCEADDRESSBANKB0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG4ZC_LDB_RAMPDWNBANKB0_ADDR_IC_1_Fast 55356
const ADI_REG_TYPE MUTEALG4ZC_LDB_RAMPDWNBANKB0_Data_IC_1_Fast[MUTEALG4ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4RAMPUPBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG4RAMPUPBANKB0_ADDR_IC_1_Fast 55612
const ADI_REG_TYPE MUTEALG4RAMPUPBANKB0_Data_IC_1_Fast[MUTEALG4RAMPUPBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4GAIN_TARGETBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG4GAIN_TARGETBANKB0_ADDR_IC_1_Fast 55868
const ADI_REG_TYPE MUTEALG4GAIN_TARGETBANKB0_Data_IC_1_Fast[MUTEALG4GAIN_TARGETBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4SOURCEADDRESSBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG4SOURCEADDRESSBANKC0_ADDR_IC_1_Fast 56124
const ADI_REG_TYPE MUTEALG4SOURCEADDRESSBANKC0_Data_IC_1_Fast[MUTEALG4SOURCEADDRESSBANKC0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG4ZC_LDB_RAMPDWNBANKC0_ADDR_IC_1_Fast 56636
const ADI_REG_TYPE MUTEALG4ZC_LDB_RAMPDWNBANKC0_Data_IC_1_Fast[MUTEALG4ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4RAMPUPBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG4RAMPUPBANKC0_ADDR_IC_1_Fast 56892
const ADI_REG_TYPE MUTEALG4RAMPUPBANKC0_Data_IC_1_Fast[MUTEALG4RAMPUPBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG4GAIN_TARGETBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG4GAIN_TARGETBANKC0_ADDR_IC_1_Fast 57148
const ADI_REG_TYPE MUTEALG4GAIN_TARGETBANKC0_Data_IC_1_Fast[MUTEALG4GAIN_TARGETBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKA0_ADDR_IC_1_Fast 53504
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x8A, 0x4D, 0x9E, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKA0_ADDR_IC_1_Fast 53760
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKA0_SIZE_IC_1_Fast] = {
0xFA, 0xF2, 0x58, 0x6C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKA0_ADDR_IC_1_Fast 54016
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x83, 0x5B, 0x12, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKA0_ADDR_IC_1_Fast 54272
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKA0_SIZE_IC_1_Fast] = {
0x0F, 0xFA, 0xE5, 0x23, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKA0_ADDR_IC_1_Fast 54528
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKA0_SIZE_IC_1_Fast] = {
0xF8, 0x05, 0x17, 0x5D, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKB0_ADDR_IC_1_Fast 54784
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKB0_ADDR_IC_1_Fast 55040
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKB0_ADDR_IC_1_Fast 55296
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKB0_ADDR_IC_1_Fast 55552
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKB0_ADDR_IC_1_Fast 55808
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKC0_ADDR_IC_1_Fast 56064
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKC0_ADDR_IC_1_Fast 56320
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKC0_ADDR_IC_1_Fast 56576
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKC0_ADDR_IC_1_Fast 56832
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKC0_ADDR_IC_1_Fast 57088
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKA1_ADDR_IC_1_Fast 53508
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKA1_SIZE_IC_1_Fast] = {
0x08, 0x1D, 0x02, 0x93, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKA1_ADDR_IC_1_Fast 53764
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKA1_SIZE_IC_1_Fast] = {
0xF0, 0x0B, 0xF6, 0x1C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKA1_ADDR_IC_1_Fast 54020
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKA1_SIZE_IC_1_Fast] = {
0x07, 0xD7, 0x48, 0xCD, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKA1_ADDR_IC_1_Fast 54276
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKA1_SIZE_IC_1_Fast] = {
0x0F, 0xF4, 0x09, 0xE4, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKA1_ADDR_IC_1_Fast 54532
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKA1_SIZE_IC_1_Fast] = {
0xF8, 0x0B, 0xB4, 0xA1, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKB1_ADDR_IC_1_Fast 54788
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKB1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKB1_ADDR_IC_1_Fast 55044
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKB1_ADDR_IC_1_Fast 55300
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKB1_ADDR_IC_1_Fast 55556
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKB1_ADDR_IC_1_Fast 55812
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKC1_ADDR_IC_1_Fast 56068
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKC1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKC1_ADDR_IC_1_Fast 56324
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKC1_ADDR_IC_1_Fast 56580
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKC1_ADDR_IC_1_Fast 56836
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKC1_ADDR_IC_1_Fast 57092
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKA2_ADDR_IC_1_Fast 53512
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKA2_SIZE_IC_1_Fast] = {
0x07, 0x09, 0x74, 0x84, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKA2_ADDR_IC_1_Fast 53768
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKA2_SIZE_IC_1_Fast] = {
0xF2, 0x08, 0xBC, 0x88, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKA2_ADDR_IC_1_Fast 54024
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKA2_SIZE_IC_1_Fast] = {
0x06, 0xF2, 0x1E, 0xC4, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKA2_ADDR_IC_1_Fast 54280
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKA2_SIZE_IC_1_Fast] = {
0x0D, 0xF7, 0x43, 0x78, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKA2_ADDR_IC_1_Fast 54536
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKA2_SIZE_IC_1_Fast] = {
0xFA, 0x04, 0x6C, 0xB8, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKB2_ADDR_IC_1_Fast 54792
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKB2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKB2_ADDR_IC_1_Fast 55048
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKB2_ADDR_IC_1_Fast 55304
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKB2_ADDR_IC_1_Fast 55560
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKB2_ADDR_IC_1_Fast 55816
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKC2_ADDR_IC_1_Fast 56072
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKC2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKC2_ADDR_IC_1_Fast 56328
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKC2_ADDR_IC_1_Fast 56584
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKC2_ADDR_IC_1_Fast 56840
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKC2_ADDR_IC_1_Fast 57096
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKA3_ADDR_IC_1_Fast 53516
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKA3_SIZE_IC_1_Fast] = {
0x13, 0x05, 0xF1, 0x62, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKA3_ADDR_IC_1_Fast 53772
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKA3_SIZE_IC_1_Fast] = {
0xDC, 0xDB, 0x11, 0x15, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKA3_ADDR_IC_1_Fast 54028
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKA3_SIZE_IC_1_Fast] = {
0x10, 0x32, 0x86, 0x76, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKA3_ADDR_IC_1_Fast 54284
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKA3_SIZE_IC_1_Fast] = {
0x0E, 0x21, 0x62, 0x66, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKA3_ADDR_IC_1_Fast 54540
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKA3_SIZE_IC_1_Fast] = {
0xF9, 0xCB, 0x14, 0xAE, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKB3_ADDR_IC_1_Fast 54796
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKB3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKB3_ADDR_IC_1_Fast 55052
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKB3_ADDR_IC_1_Fast 55308
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKB3_ADDR_IC_1_Fast 55564
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKB3_ADDR_IC_1_Fast 55820
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN30BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN30BBANKC3_ADDR_IC_1_Fast 56076
const ADI_REG_TYPE EQ1787SINGLECHAN30BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN30BBANKC3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31BBANKC3_ADDR_IC_1_Fast 56332
const ADI_REG_TYPE EQ1787SINGLECHAN31BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN31BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32BBANKC3_ADDR_IC_1_Fast 56588
const ADI_REG_TYPE EQ1787SINGLECHAN32BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN32BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN31ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN31ABANKC3_ADDR_IC_1_Fast 56844
const ADI_REG_TYPE EQ1787SINGLECHAN31ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN31ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN32ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN32ABANKC3_ADDR_IC_1_Fast 57100
const ADI_REG_TYPE EQ1787SINGLECHAN32ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN32ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKA0_ADDR_IC_1_Fast 53548
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x8A, 0x4D, 0x9E, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKA0_ADDR_IC_1_Fast 53804
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKA0_SIZE_IC_1_Fast] = {
0xFA, 0xF2, 0x58, 0x6C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKA0_ADDR_IC_1_Fast 54060
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKA0_SIZE_IC_1_Fast] = {
0x02, 0x83, 0x5B, 0x12, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKA0_ADDR_IC_1_Fast 54316
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKA0_SIZE_IC_1_Fast] = {
0x0F, 0xFA, 0xE5, 0x23, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKA0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKA0_ADDR_IC_1_Fast 54572
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKA0_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKA0_SIZE_IC_1_Fast] = {
0xF8, 0x05, 0x17, 0x5D, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKB0_ADDR_IC_1_Fast 54828
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKB0_ADDR_IC_1_Fast 55084
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKB0_ADDR_IC_1_Fast 55340
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKB0_ADDR_IC_1_Fast 55596
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKB0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKB0_ADDR_IC_1_Fast 55852
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKB0_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKB0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKC0_ADDR_IC_1_Fast 56108
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKC0_ADDR_IC_1_Fast 56364
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKC0_ADDR_IC_1_Fast 56620
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKC0_ADDR_IC_1_Fast 56876
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKC0_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKC0_ADDR_IC_1_Fast 57132
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKC0_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKC0_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKA1_ADDR_IC_1_Fast 53552
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKA1_SIZE_IC_1_Fast] = {
0x08, 0x1D, 0x02, 0x93, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKA1_ADDR_IC_1_Fast 53808
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKA1_SIZE_IC_1_Fast] = {
0xF0, 0x0B, 0xF6, 0x1C, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKA1_ADDR_IC_1_Fast 54064
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKA1_SIZE_IC_1_Fast] = {
0x07, 0xD7, 0x48, 0xCD, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKA1_ADDR_IC_1_Fast 54320
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKA1_SIZE_IC_1_Fast] = {
0x0F, 0xF4, 0x09, 0xE4, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKA1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKA1_ADDR_IC_1_Fast 54576
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKA1_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKA1_SIZE_IC_1_Fast] = {
0xF8, 0x0B, 0xB4, 0xA1, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKB1_ADDR_IC_1_Fast 54832
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKB1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKB1_ADDR_IC_1_Fast 55088
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKB1_ADDR_IC_1_Fast 55344
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKB1_ADDR_IC_1_Fast 55600
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKB1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKB1_ADDR_IC_1_Fast 55856
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKB1_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKB1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKC1_ADDR_IC_1_Fast 56112
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKC1_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKC1_ADDR_IC_1_Fast 56368
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKC1_ADDR_IC_1_Fast 56624
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKC1_ADDR_IC_1_Fast 56880
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKC1_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKC1_ADDR_IC_1_Fast 57136
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKC1_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKC1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKA2_ADDR_IC_1_Fast 53556
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKA2_SIZE_IC_1_Fast] = {
0x07, 0x09, 0x74, 0x84, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKA2_ADDR_IC_1_Fast 53812
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKA2_SIZE_IC_1_Fast] = {
0xF2, 0x08, 0xBC, 0x88, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKA2_ADDR_IC_1_Fast 54068
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKA2_SIZE_IC_1_Fast] = {
0x06, 0xF2, 0x1E, 0xC4, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKA2_ADDR_IC_1_Fast 54324
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKA2_SIZE_IC_1_Fast] = {
0x0D, 0xF7, 0x43, 0x78, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKA2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKA2_ADDR_IC_1_Fast 54580
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKA2_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKA2_SIZE_IC_1_Fast] = {
0xFA, 0x04, 0x6C, 0xB8, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKB2_ADDR_IC_1_Fast 54836
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKB2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKB2_ADDR_IC_1_Fast 55092
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKB2_ADDR_IC_1_Fast 55348
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKB2_ADDR_IC_1_Fast 55604
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKB2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKB2_ADDR_IC_1_Fast 55860
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKB2_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKB2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKC2_ADDR_IC_1_Fast 56116
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKC2_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKC2_ADDR_IC_1_Fast 56372
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKC2_ADDR_IC_1_Fast 56628
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKC2_ADDR_IC_1_Fast 56884
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKC2_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKC2_ADDR_IC_1_Fast 57140
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKC2_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKC2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKA3_ADDR_IC_1_Fast 53560
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKA3_SIZE_IC_1_Fast] = {
0x13, 0x05, 0xF1, 0x62, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKA3_ADDR_IC_1_Fast 53816
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKA3_SIZE_IC_1_Fast] = {
0xDC, 0xDB, 0x11, 0x15, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKA3_ADDR_IC_1_Fast 54072
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKA3_SIZE_IC_1_Fast] = {
0x10, 0x32, 0x86, 0x76, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKA3_ADDR_IC_1_Fast 54328
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKA3_SIZE_IC_1_Fast] = {
0x0E, 0x21, 0x62, 0x66, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKA3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKA3_ADDR_IC_1_Fast 54584
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKA3_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKA3_SIZE_IC_1_Fast] = {
0xF9, 0xCB, 0x14, 0xAE, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKB3_ADDR_IC_1_Fast 54840
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKB3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKB3_ADDR_IC_1_Fast 55096
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKB3_ADDR_IC_1_Fast 55352
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKB3_ADDR_IC_1_Fast 55608
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKB3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKB3_ADDR_IC_1_Fast 55864
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKB3_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKB3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN40BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN40BBANKC3_ADDR_IC_1_Fast 56120
const ADI_REG_TYPE EQ1787SINGLECHAN40BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN40BBANKC3_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41BBANKC3_ADDR_IC_1_Fast 56376
const ADI_REG_TYPE EQ1787SINGLECHAN41BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN41BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42BBANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42BBANKC3_ADDR_IC_1_Fast 56632
const ADI_REG_TYPE EQ1787SINGLECHAN42BBANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN42BBANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN41ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN41ABANKC3_ADDR_IC_1_Fast 56888
const ADI_REG_TYPE EQ1787SINGLECHAN41ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN41ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define EQ1787SINGLECHAN42ABANKC3_SIZE_IC_1_Fast 4
#define EQ1787SINGLECHAN42ABANKC3_ADDR_IC_1_Fast 57144
const ADI_REG_TYPE EQ1787SINGLECHAN42ABANKC3_Data_IC_1_Fast[EQ1787SINGLECHAN42ABANKC3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1SOURCEADDRESSBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG1SOURCEADDRESSBANKA0_ADDR_IC_1_Fast 53588
const ADI_REG_TYPE MUTEALG1SOURCEADDRESSBANKA0_Data_IC_1_Fast[MUTEALG1SOURCEADDRESSBANKA0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG1ZC_LDB_RAMPDWNBANKA0_ADDR_IC_1_Fast 54100
const ADI_REG_TYPE MUTEALG1ZC_LDB_RAMPDWNBANKA0_Data_IC_1_Fast[MUTEALG1ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1RAMPUPBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG1RAMPUPBANKA0_ADDR_IC_1_Fast 54356
const ADI_REG_TYPE MUTEALG1RAMPUPBANKA0_Data_IC_1_Fast[MUTEALG1RAMPUPBANKA0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x04, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1GAIN_TARGETBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG1GAIN_TARGETBANKA0_ADDR_IC_1_Fast 54612
const ADI_REG_TYPE MUTEALG1GAIN_TARGETBANKA0_Data_IC_1_Fast[MUTEALG1GAIN_TARGETBANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1SOURCEADDRESSBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG1SOURCEADDRESSBANKB0_ADDR_IC_1_Fast 54868
const ADI_REG_TYPE MUTEALG1SOURCEADDRESSBANKB0_Data_IC_1_Fast[MUTEALG1SOURCEADDRESSBANKB0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG1ZC_LDB_RAMPDWNBANKB0_ADDR_IC_1_Fast 55380
const ADI_REG_TYPE MUTEALG1ZC_LDB_RAMPDWNBANKB0_Data_IC_1_Fast[MUTEALG1ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1RAMPUPBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG1RAMPUPBANKB0_ADDR_IC_1_Fast 55636
const ADI_REG_TYPE MUTEALG1RAMPUPBANKB0_Data_IC_1_Fast[MUTEALG1RAMPUPBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1GAIN_TARGETBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG1GAIN_TARGETBANKB0_ADDR_IC_1_Fast 55892
const ADI_REG_TYPE MUTEALG1GAIN_TARGETBANKB0_Data_IC_1_Fast[MUTEALG1GAIN_TARGETBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1SOURCEADDRESSBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG1SOURCEADDRESSBANKC0_ADDR_IC_1_Fast 56148
const ADI_REG_TYPE MUTEALG1SOURCEADDRESSBANKC0_Data_IC_1_Fast[MUTEALG1SOURCEADDRESSBANKC0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG1ZC_LDB_RAMPDWNBANKC0_ADDR_IC_1_Fast 56660
const ADI_REG_TYPE MUTEALG1ZC_LDB_RAMPDWNBANKC0_Data_IC_1_Fast[MUTEALG1ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1RAMPUPBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG1RAMPUPBANKC0_ADDR_IC_1_Fast 56916
const ADI_REG_TYPE MUTEALG1RAMPUPBANKC0_Data_IC_1_Fast[MUTEALG1RAMPUPBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG1GAIN_TARGETBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG1GAIN_TARGETBANKC0_ADDR_IC_1_Fast 57172
const ADI_REG_TYPE MUTEALG1GAIN_TARGETBANKC0_Data_IC_1_Fast[MUTEALG1GAIN_TARGETBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2SOURCEADDRESSBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG2SOURCEADDRESSBANKA0_ADDR_IC_1_Fast 53544
const ADI_REG_TYPE MUTEALG2SOURCEADDRESSBANKA0_Data_IC_1_Fast[MUTEALG2SOURCEADDRESSBANKA0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG2ZC_LDB_RAMPDWNBANKA0_ADDR_IC_1_Fast 54056
const ADI_REG_TYPE MUTEALG2ZC_LDB_RAMPDWNBANKA0_Data_IC_1_Fast[MUTEALG2ZC_LDB_RAMPDWNBANKA0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2RAMPUPBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG2RAMPUPBANKA0_ADDR_IC_1_Fast 54312
const ADI_REG_TYPE MUTEALG2RAMPUPBANKA0_Data_IC_1_Fast[MUTEALG2RAMPUPBANKA0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x04, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2GAIN_TARGETBANKA0_SIZE_IC_1_Fast 4
#define MUTEALG2GAIN_TARGETBANKA0_ADDR_IC_1_Fast 54568
const ADI_REG_TYPE MUTEALG2GAIN_TARGETBANKA0_Data_IC_1_Fast[MUTEALG2GAIN_TARGETBANKA0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2SOURCEADDRESSBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG2SOURCEADDRESSBANKB0_ADDR_IC_1_Fast 54824
const ADI_REG_TYPE MUTEALG2SOURCEADDRESSBANKB0_Data_IC_1_Fast[MUTEALG2SOURCEADDRESSBANKB0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG2ZC_LDB_RAMPDWNBANKB0_ADDR_IC_1_Fast 55336
const ADI_REG_TYPE MUTEALG2ZC_LDB_RAMPDWNBANKB0_Data_IC_1_Fast[MUTEALG2ZC_LDB_RAMPDWNBANKB0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2RAMPUPBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG2RAMPUPBANKB0_ADDR_IC_1_Fast 55592
const ADI_REG_TYPE MUTEALG2RAMPUPBANKB0_Data_IC_1_Fast[MUTEALG2RAMPUPBANKB0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2GAIN_TARGETBANKB0_SIZE_IC_1_Fast 4
#define MUTEALG2GAIN_TARGETBANKB0_ADDR_IC_1_Fast 55848
const ADI_REG_TYPE MUTEALG2GAIN_TARGETBANKB0_Data_IC_1_Fast[MUTEALG2GAIN_TARGETBANKB0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2SOURCEADDRESSBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG2SOURCEADDRESSBANKC0_ADDR_IC_1_Fast 56104
const ADI_REG_TYPE MUTEALG2SOURCEADDRESSBANKC0_Data_IC_1_Fast[MUTEALG2SOURCEADDRESSBANKC0_SIZE_IC_1_Fast] = {
0xC9, 0xF0, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG2ZC_LDB_RAMPDWNBANKC0_ADDR_IC_1_Fast 56616
const ADI_REG_TYPE MUTEALG2ZC_LDB_RAMPDWNBANKC0_Data_IC_1_Fast[MUTEALG2ZC_LDB_RAMPDWNBANKC0_SIZE_IC_1_Fast] = {
0x01, 0x7F, 0xFC, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2RAMPUPBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG2RAMPUPBANKC0_ADDR_IC_1_Fast 56872
const ADI_REG_TYPE MUTEALG2RAMPUPBANKC0_Data_IC_1_Fast[MUTEALG2RAMPUPBANKC0_SIZE_IC_1_Fast] = {
0x00, 0x80, 0x00, 0x00, 
};

/* DSP Ram Data */
#define MUTEALG2GAIN_TARGETBANKC0_SIZE_IC_1_Fast 4
#define MUTEALG2GAIN_TARGETBANKC0_ADDR_IC_1_Fast 57128
const ADI_REG_TYPE MUTEALG2GAIN_TARGETBANKC0_Data_IC_1_Fast[MUTEALG2GAIN_TARGETBANKC0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_A_PARAMETER_0_SIZE_IC_1_Fast 112
#define BANK_A_PARAMETER_0_ADDR_IC_1_Fast 53504
const ADI_REG_TYPE BANK_A_PARAMETER_0_IC_1_Fast[BANK_A_PARAMETER_0_SIZE_IC_1_Fast] = {
0x02, 0x8A, 0x4D, 0x9E, 0x08, 
0x1D, 0x02, 0x93, 0x07, 0x09, 
0x74, 0x84, 0x13, 0x05, 0xF1, 
0x62, 0xC9, 0xF0, 0x00, 0x00, 
0x02, 0x89, 0x16, 0x37, 0x07, 
0xF8, 0xF6, 0x26, 0x07, 0xDF, 
0xE4, 0x8B, 0x07, 0x01, 0xDC, 
0x6C, 0x05, 0x5F, 0x47, 0x73, 
0xC9, 0xF0, 0x00, 0x00, 0x02, 
0x8A, 0x4D, 0x9E, 0x08, 0x1D, 
0x02, 0x93, 0x07, 0x09, 0x74, 
0x84, 0x13, 0x05, 0xF1, 0x62, 
0xC9, 0xF0, 0x00, 0x00, 0x02, 
0x89, 0x16, 0x37, 0x07, 0xF8, 
0xF6, 0x26, 0x07, 0xDF, 0xE4, 
0x8B, 0x07, 0x01, 0xDC, 0x6C, 
0x05, 0x5F, 0x47, 0x73, 0xC9, 
0xF0, 0x00, 0x00, 0xD1, 0xA4, 
0x67, 0xD0, 0xC8, 0x00, 0x00, 
0x00, 0xD5, 0xAC, 0x6F, 0xD0, 
0xCA, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_A_PARAMETER_1_SIZE_IC_1_Fast 112
#define BANK_A_PARAMETER_1_ADDR_IC_1_Fast 53760
const ADI_REG_TYPE BANK_A_PARAMETER_1_IC_1_Fast[BANK_A_PARAMETER_1_SIZE_IC_1_Fast] = {
0xFA, 0xF2, 0x58, 0x6C, 0xF0, 
0x0B, 0xF6, 0x1C, 0xF2, 0x08, 
0xBC, 0x88, 0xDC, 0xDB, 0x11, 
0x15, 0x00, 0x00, 0x00, 0x00, 
0xFA, 0xF5, 0x57, 0x34, 0xF0, 
0x14, 0x98, 0x82, 0xF0, 0x60, 
0x64, 0x95, 0xF2, 0x4B, 0xDD, 
0x64, 0xF7, 0x62, 0x09, 0xE7, 
0x00, 0x00, 0x00, 0x00, 0xFA, 
0xF2, 0x58, 0x6C, 0xF0, 0x0B, 
0xF6, 0x1C, 0xF2, 0x08, 0xBC, 
0x88, 0xDC, 0xDB, 0x11, 0x15, 
0x00, 0x00, 0x00, 0x00, 0xFA, 
0xF5, 0x57, 0x34, 0xF0, 0x14, 
0x98, 0x82, 0xF0, 0x60, 0x64, 
0x95, 0xF2, 0x4B, 0xDD, 0x64, 
0xF7, 0x62, 0x09, 0xE7, 0x00, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_A_PARAMETER_2_SIZE_IC_1_Fast 112
#define BANK_A_PARAMETER_2_ADDR_IC_1_Fast 54016
const ADI_REG_TYPE BANK_A_PARAMETER_2_IC_1_Fast[BANK_A_PARAMETER_2_SIZE_IC_1_Fast] = {
0x02, 0x83, 0x5B, 0x12, 0x07, 
0xD7, 0x48, 0xCD, 0x06, 0xF2, 
0x1E, 0xC4, 0x10, 0x32, 0x86, 
0x76, 0x01, 0x7F, 0xFC, 0x00, 
0x02, 0x81, 0xA5, 0xDA, 0x07, 
0xF2, 0x73, 0x87, 0x07, 0xC1, 
0x2C, 0x26, 0x06, 0xBD, 0x4D, 
0xD7, 0x03, 0x74, 0x98, 0x91, 
0x01, 0x7F, 0xFC, 0x00, 0x02, 
0x83, 0x5B, 0x12, 0x07, 0xD7, 
0x48, 0xCD, 0x06, 0xF2, 0x1E, 
0xC4, 0x10, 0x32, 0x86, 0x76, 
0x01, 0x7F, 0xFC, 0x00, 0x02, 
0x81, 0xA5, 0xDA, 0x07, 0xF2, 
0x73, 0x87, 0x07, 0xC1, 0x2C, 
0x26, 0x06, 0xBD, 0x4D, 0xD7, 
0x03, 0x74, 0x98, 0x91, 0x01, 
0x7F, 0xFC, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_A_PARAMETER_3_SIZE_IC_1_Fast 112
#define BANK_A_PARAMETER_3_ADDR_IC_1_Fast 54272
const ADI_REG_TYPE BANK_A_PARAMETER_3_IC_1_Fast[BANK_A_PARAMETER_3_SIZE_IC_1_Fast] = {
0x0F, 0xFA, 0xE5, 0x23, 0x0F, 
0xF4, 0x09, 0xE4, 0x0D, 0xF7, 
0x43, 0x78, 0x0E, 0x21, 0x62, 
0x66, 0x00, 0x80, 0x04, 0x00, 
0x0F, 0xF1, 0x6C, 0x5D, 0x0F, 
0xEB, 0x67, 0x7E, 0x0F, 0x9F, 
0x9B, 0x6B, 0x0D, 0xB4, 0x22, 
0x9C, 0x0D, 0x67, 0x6C, 0x87, 
0x00, 0x80, 0x04, 0x00, 0x0F, 
0xFA, 0xE5, 0x23, 0x0F, 0xF4, 
0x09, 0xE4, 0x0D, 0xF7, 0x43, 
0x78, 0x0E, 0x21, 0x62, 0x66, 
0x00, 0x80, 0x04, 0x00, 0x0F, 
0xF1, 0x6C, 0x5D, 0x0F, 0xEB, 
0x67, 0x7E, 0x0F, 0x9F, 0x9B, 
0x6B, 0x0D, 0xB4, 0x22, 0x9C, 
0x0D, 0x67, 0x6C, 0x87, 0x00, 
0x80, 0x04, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_A_PARAMETER_4_SIZE_IC_1_Fast 112
#define BANK_A_PARAMETER_4_ADDR_IC_1_Fast 54528
const ADI_REG_TYPE BANK_A_PARAMETER_4_IC_1_Fast[BANK_A_PARAMETER_4_SIZE_IC_1_Fast] = {
0xF8, 0x05, 0x17, 0x5D, 0xF8, 
0x0B, 0xB4, 0xA1, 0xFA, 0x04, 
0x6C, 0xB8, 0xF9, 0xCB, 0x14, 
0xAE, 0x08, 0x00, 0x00, 0x00, 
0xF8, 0x0E, 0x56, 0xB5, 0xF8, 
0x14, 0x96, 0x53, 0xF8, 0x5E, 
0xEF, 0x4F, 0xFA, 0x40, 0xD5, 
0xBE, 0xFA, 0x62, 0xA9, 0x8F, 
0x08, 0x00, 0x00, 0x00, 0xF8, 
0x05, 0x17, 0x5D, 0xF8, 0x0B, 
0xB4, 0xA1, 0xFA, 0x04, 0x6C, 
0xB8, 0xF9, 0xCB, 0x14, 0xAE, 
0x08, 0x00, 0x00, 0x00, 0xF8, 
0x0E, 0x56, 0xB5, 0xF8, 0x14, 
0x96, 0x53, 0xF8, 0x5E, 0xEF, 
0x4F, 0xFA, 0x40, 0xD5, 0xBE, 
0xFA, 0x62, 0xA9, 0x8F, 0x08, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_B_PARAMETER_0_SIZE_IC_1_Fast 112
#define BANK_B_PARAMETER_0_ADDR_IC_1_Fast 54784
const ADI_REG_TYPE BANK_B_PARAMETER_0_IC_1_Fast[BANK_B_PARAMETER_0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0xC9, 0xF0, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0xC9, 0xF0, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0xC9, 0xF0, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0xC9, 
0xF0, 0x00, 0x00, 0xD1, 0xA4, 
0x67, 0xD0, 0xC8, 0x00, 0x00, 
0x00, 0xD5, 0xAC, 0x6F, 0xD0, 
0xCA, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_B_PARAMETER_1_SIZE_IC_1_Fast 112
#define BANK_B_PARAMETER_1_ADDR_IC_1_Fast 55040
const ADI_REG_TYPE BANK_B_PARAMETER_1_IC_1_Fast[BANK_B_PARAMETER_1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_B_PARAMETER_2_SIZE_IC_1_Fast 112
#define BANK_B_PARAMETER_2_ADDR_IC_1_Fast 55296
const ADI_REG_TYPE BANK_B_PARAMETER_2_IC_1_Fast[BANK_B_PARAMETER_2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x01, 0x7F, 0xFC, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x01, 0x7F, 0xFC, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x01, 0x7F, 0xFC, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x01, 
0x7F, 0xFC, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_B_PARAMETER_3_SIZE_IC_1_Fast 112
#define BANK_B_PARAMETER_3_ADDR_IC_1_Fast 55552
const ADI_REG_TYPE BANK_B_PARAMETER_3_IC_1_Fast[BANK_B_PARAMETER_3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x80, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x80, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x80, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x80, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_B_PARAMETER_4_SIZE_IC_1_Fast 112
#define BANK_B_PARAMETER_4_ADDR_IC_1_Fast 55808
const ADI_REG_TYPE BANK_B_PARAMETER_4_IC_1_Fast[BANK_B_PARAMETER_4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_C_PARAMETER_0_SIZE_IC_1_Fast 112
#define BANK_C_PARAMETER_0_ADDR_IC_1_Fast 56064
const ADI_REG_TYPE BANK_C_PARAMETER_0_IC_1_Fast[BANK_C_PARAMETER_0_SIZE_IC_1_Fast] = {
0x08, 0x00, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0xC9, 0xF0, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0xC9, 0xF0, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0xC9, 0xF0, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x08, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0xC9, 
0xF0, 0x00, 0x00, 0xD1, 0xA4, 
0x67, 0xD0, 0xC8, 0x00, 0x00, 
0x00, 0xD5, 0xAC, 0x6F, 0xD0, 
0xCA, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_C_PARAMETER_1_SIZE_IC_1_Fast 112
#define BANK_C_PARAMETER_1_ADDR_IC_1_Fast 56320
const ADI_REG_TYPE BANK_C_PARAMETER_1_IC_1_Fast[BANK_C_PARAMETER_1_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_C_PARAMETER_2_SIZE_IC_1_Fast 112
#define BANK_C_PARAMETER_2_ADDR_IC_1_Fast 56576
const ADI_REG_TYPE BANK_C_PARAMETER_2_IC_1_Fast[BANK_C_PARAMETER_2_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x01, 0x7F, 0xFC, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x01, 0x7F, 0xFC, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x01, 0x7F, 0xFC, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x01, 
0x7F, 0xFC, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_C_PARAMETER_3_SIZE_IC_1_Fast 112
#define BANK_C_PARAMETER_3_ADDR_IC_1_Fast 56832
const ADI_REG_TYPE BANK_C_PARAMETER_3_IC_1_Fast[BANK_C_PARAMETER_3_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x80, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x80, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x80, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x80, 0x00, 0x00, 0x08, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Ram Data */
#define BANK_C_PARAMETER_4_SIZE_IC_1_Fast 112
#define BANK_C_PARAMETER_4_ADDR_IC_1_Fast 57088
const ADI_REG_TYPE BANK_C_PARAMETER_4_IC_1_Fast[BANK_C_PARAMETER_4_SIZE_IC_1_Fast] = {
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x08, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x08, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x08, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};

/* DSP Program Data */
#define PROGRAM_SIZE_IC_1_Fast 112
#define PROGRAM_ADDR_IC_1_Fast 53248
const ADI_REG_TYPE Program_Data_IC_1_Fast[PROGRAM_SIZE_IC_1_Fast] = {
0x00, 0xC0, 0x48, 0x00, 0x00, 
0xF2, 0x48, 0x00, 0x00, 0xF2, 
0x48, 0x00, 0x00, 0xF2, 0x48, 
0x00, 0x01, 0x80, 0x50, 0x00, 
0x00, 0xC0, 0xC8, 0x00, 0x00, 
0xF2, 0x48, 0x00, 0x00, 0xF2, 
0x48, 0x00, 0x00, 0xF2, 0x48, 
0x00, 0x00, 0xF2, 0x48, 0x00, 
0x01, 0x80, 0x52, 0x00, 0x00, 
0xC1, 0x48, 0x00, 0x00, 0xF2, 
0x48, 0x00, 0x00, 0xF2, 0x48, 
0x00, 0x00, 0xF2, 0x48, 0x00, 
0x01, 0x80, 0x54, 0x00, 0x00, 
0xC1, 0xC8, 0x00, 0x00, 0xF2, 
0x48, 0x00, 0x00, 0xF2, 0x48, 
0x00, 0x00, 0xF2, 0x48, 0x00, 
0x00, 0xF2, 0x48, 0x00, 0x01, 
0x80, 0x56, 0x00, 0x01, 0xC0, 
0x48, 0x00, 0x04, 0x80, 0x00, 
0x00, 0x01, 0xC0, 0x4A, 0x00, 
0x04, 0x80, 0x02, 0x00, 0x00, 
0x00, 0x00, 0x00, 0x00, 0x00, 
0x00, 0x00, 
};


/* Register Default - IC 1-Fast.FDSP_RUN */
const ADI_REG_TYPE R0_FDSP_RUN_IC_1_Fast_Default[REG_FDSP_RUN_IC_1_Fast_BYTE] = {
0x00
};

/* Register Default - IC 1-Fast.FDSP_RUN */
const ADI_REG_TYPE R17_FDSP_RUN_IC_1_Fast_Default[REG_FDSP_RUN_IC_1_Fast_BYTE] = {
0x01
};


/*
 * Default Download
 */
#define DEFAULT_DOWNLOAD_SIZE_IC_1_Fast 18

void default_download_IC_1_Fast() {
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, REG_FDSP_RUN_IC_1_Fast_ADDR, REG_FDSP_RUN_IC_1_Fast_BYTE, R0_FDSP_RUN_IC_1_Fast_Default );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, PROGRAM_ADDR_IC_1_Fast, PROGRAM_SIZE_IC_1_Fast, Program_Data_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_A_PARAMETER_0_ADDR_IC_1_Fast, BANK_A_PARAMETER_0_SIZE_IC_1_Fast, BANK_A_PARAMETER_0_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_A_PARAMETER_1_ADDR_IC_1_Fast, BANK_A_PARAMETER_1_SIZE_IC_1_Fast, BANK_A_PARAMETER_1_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_A_PARAMETER_2_ADDR_IC_1_Fast, BANK_A_PARAMETER_2_SIZE_IC_1_Fast, BANK_A_PARAMETER_2_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_A_PARAMETER_3_ADDR_IC_1_Fast, BANK_A_PARAMETER_3_SIZE_IC_1_Fast, BANK_A_PARAMETER_3_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_A_PARAMETER_4_ADDR_IC_1_Fast, BANK_A_PARAMETER_4_SIZE_IC_1_Fast, BANK_A_PARAMETER_4_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_B_PARAMETER_0_ADDR_IC_1_Fast, BANK_B_PARAMETER_0_SIZE_IC_1_Fast, BANK_B_PARAMETER_0_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_B_PARAMETER_1_ADDR_IC_1_Fast, BANK_B_PARAMETER_1_SIZE_IC_1_Fast, BANK_B_PARAMETER_1_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_B_PARAMETER_2_ADDR_IC_1_Fast, BANK_B_PARAMETER_2_SIZE_IC_1_Fast, BANK_B_PARAMETER_2_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_B_PARAMETER_3_ADDR_IC_1_Fast, BANK_B_PARAMETER_3_SIZE_IC_1_Fast, BANK_B_PARAMETER_3_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_B_PARAMETER_4_ADDR_IC_1_Fast, BANK_B_PARAMETER_4_SIZE_IC_1_Fast, BANK_B_PARAMETER_4_IC_1_Fast );
	// SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_C_PARAMETER_0_ADDR_IC_1_Fast, BANK_C_PARAMETER_0_SIZE_IC_1_Fast, BANK_C_PARAMETER_0_IC_1_Fast );
	// SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_C_PARAMETER_1_ADDR_IC_1_Fast, BANK_C_PARAMETER_1_SIZE_IC_1_Fast, BANK_C_PARAMETER_1_IC_1_Fast );
	// SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_C_PARAMETER_2_ADDR_IC_1_Fast, BANK_C_PARAMETER_2_SIZE_IC_1_Fast, BANK_C_PARAMETER_2_IC_1_Fast );
	// SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_C_PARAMETER_3_ADDR_IC_1_Fast, BANK_C_PARAMETER_3_SIZE_IC_1_Fast, BANK_C_PARAMETER_3_IC_1_Fast );
	// SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, BANK_C_PARAMETER_4_ADDR_IC_1_Fast, BANK_C_PARAMETER_4_SIZE_IC_1_Fast, BANK_C_PARAMETER_4_IC_1_Fast );
	SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1_FAST, REG_FDSP_RUN_IC_1_Fast_ADDR, REG_FDSP_RUN_IC_1_Fast_BYTE, R17_FDSP_RUN_IC_1_Fast_Default );
}

#endif
